A rectilinear Steiner tree (RST) is a fundamental structure that may be used to model interconnects between nodes. A rectilinear Steiner minimum tree (RSMT) aims to minimize the wire length. Various algorithms have been developed to construct a RSMT. For example, BI1S, BOI and FLUTE are near-optimal RSMT heuristics while GeoSteiner is optimal with reasonable runtime for small trees. A large fraction of nets in multi-GHz microprocessors and other reasonably high frequency chips need buffering for mitigating large signal slew (transition time) and delay. Timing-driven Steiner tree construction is, thus, of paramount importance in these applications. Various approaches focus on the minimum (pre-buffer) delay routing tree (MDRT) problem, which minimizes a linear combination of delays at sinks Other approaches optimize the required arrival time at the driver with power/timing trade-offs and wire sizing. A minimum rectilinear Steiner arborescence (MRSA) (which is an RST such that each source-to-sink path is a shortest path) improves the performance (3%-5%) with slightly higher wire-length. However, buffering an optimized un-buffered tree may undo the order of sink criticalities. The path from the source to a critical sink may incur more delay due to the number of buffers placed in the path.